The present disclosure relates to signal line sensing and, more particularly, to single-ended sensing circuits configured for relatively fast pre-charging operations and relatively fast and accurate sensing operations.
Memory circuits, such as content addressable memory (CAM) circuits, dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, etc., often incorporate single-ended sensing circuits to sense the value of a signal and, particularly, a small signal on a signal line (e.g., a match line in the case of a CAM circuit, a bit line in the case of a DRAM circuit, a bit line in the case of an SRAM circuit, etc.). Those skilled in the art will recognize that the term “single-ended” refers to the fact that the sensing circuits sense the value of a signal on a single signal line input into a sense amplifier as opposed to comparing the values of signals on two separate signal lines input into a sense amplifier. Recently, technology scaling (e.g., to sub-100 nm dimensions) has resulted in relatively large random variations in manufactured semiconductor devices incorporated into such memory circuits and, particularly, has resulted in relatively large random threshold voltage (Vt) variations in manufactured field effect transistors (FETs) incorporated into such memory circuits. To compensate for these variations, sensing circuits typically operate with pessimistic timing margins, which degrade performance. Therefore, there is a need in the art for an improved single-ended sensing circuit that compensates for semiconductor device variations and, particularly, FET threshold voltage (Vt) variations with minimal performance degradation.